Power amplifiers in mobile handsets are typically stand-alone structures due to the difficulty in simultaneously achieving high power, high efficiency, and high linearity in the low-cost CMOS processes (or structures) used for the rest of the communications circuitry. Since power amplifiers are a significant drain on battery power in a mobile handset, the efficiency of a power amplifier should be maximized in the circuitry at a variety of power levels necessary for typical operation. However, in general, single path power amplifiers trade off linearity for increased efficiency, and are considered efficient only at peak output levels. In contrast, a Doherty amplifier configuration (also referred to herein as simply the “Doherty amplifier”) allows for increased efficiency at levels lower than maximum output power by dynamically changing the load seen by part of the amplifier.
The Doherty amplifier includes a primary (carrier) amplifier that is placed in parallel with an auxiliary (peaking) amplifier or amplifiers. In the operation of a Doherty amplifier, the modulated load forces the carrier amplifier to reach its maximum voltage swing sooner, resulting in greater efficiency. The peaking amplifier is gradually turned on as input levels to the Doherty amplifier rise. A quarter wave transformer at the output of the primary path prevents the voltage swing of the carrier amplifier from becoming too large. Thus, efficiency is maintained without sacrificing linearity.
FIG. 1 illustrates a common configuration for a Doherty amplifier that includes a carrier amplifier 101 and a peaking amplifier 102 in parallel. As shown in FIG. 1, a power splitter 105 divides the power evenly between each path while a quarter wave transformer 103 is used to assist in modulating the carrier amplifier 101 load impedance. To equalize the path delay an additional quarter wave transformer 104 is placed before the peaking amplifier 102.
The gradual “turning on” of the peaking amplifier in a Doherty amplifier configuration is generally achieved by biasing transistors so that they operate below a threshold voltage level in order for appreciable current to flow, a bias point referred to as Class C. A Class C amplifier contributes a great deal of non-linearity due to its reduced conduction angle. In a typically non-linear process (or structure) such as CMOS, such non-linear operation of the amplifier(s) is unacceptable due to stringent linearity and power requirements in modern wireless communication standards. Moreover, a higher bias point reduces the efficiency of the Doherty amplifier by modulating the load at too low of an input power and thus preventing the carrier amplifier from reaching a maximal voltage swing. Therefore, the concept of adaptive bias is an attractive way to improve linearity without sacrificing current consumption or efficiency at output power levels less than maximum, such levels are generally referred to as back-off levels.
Heterojunction bipolar transistors (HBTs) dominate the power amplifier market. A self-biasing effect in bipolar junction transistors reduces the input impedance of a device as input power increases due to temperature effects. As set forth in Doherty Linear Power Amplifiers for Mobile Handset Applications, Kim et al., IEEE Proceedings of Asia-Pacific Microwave Conference 2006, one advantage of this impedance change is the possibility to employ dynamically uneven power drive. In this topology, illustrated in FIG. 2, the bulky power splitter 105 of the common Doherty amplifier configuration shown in FIG. 1 is removed from the design and replaced by additional (at or about) (“substantially”) 90 degree lines along each path to take advantage of this effect, pushing more current to the more efficient peaking amplifier as input power increases. The opposite effect has been shown to occur in CMOS transistors, although the desired effect can be mimicked with a gradually increasing bias, at the expense of efficiency. As shown in FIG. 2, the carrier amplifier 201 and peaking amplifier 202 are now preceded by a quarter wave transformer 204 and a half wave transformer 205, respectively. Moreover, as shown in FIG. 2, a quarter wave transformer 203 follows the carrier amplifier as in FIG. 1.
Although uneven power drive appears attractive in terms of efficiency, layout area is not significantly reduced at cellular frequencies since transmission lines are not feasible, and therefore lumped element equivalents must be used. In general, a collection of passive components creating, for instance, a quarter wave transformer is called a lumped element equivalent circuit. Furthermore, in CMOS processes (or structures), linearity complications arise making it unattractive to implement dynamically uneven power drive as the desired efficiency gains must be sacrificed. Another complication in CMOS is low breakdown voltage compared to dominant power amplifier technologies. This deficiency leads to several topological choices, particularly a differential cascode structure. Typically the output and input baluns necessary for differential operation are large on-chip structures. In addition to the two lumped element quarter wave transformers necessary for Doherty amplifier operation, the area of these structures makes the topology highly inefficient with respect to layout area. What is needed is a way to reduce layout area space consumed with minimal sacrificing to performance.